This invention relates to a semiconductor memory device and its testing technology, and more particularly to a technology which is effective, for example, when applied to test a dynamic random access memory (hereinafter called as DRAM or a dynamic type RAM).
In the course of recent developments in semiconductor technology, DRAMs having a large memory capacity such as about 1M bit have been developed. As memory capacity is increased, testing time for the memory is correspondingly increased. Therefore, it has been proposed to provide a DRAM in which a testing circuit is arranged within the DRAM. In the proposed system, similar signals are already written in its memory array with a unit of x4 bits, and an external output terminal becomes a high impedance if any one bit of x4 bits signal read out of the memory array does not coincide with the remaining signals. In this case, if all the reading signals of x4 bits are in a high level or a low level, either a high level signal or a low level signal is outputted from the output terminal. (See "Mitsubishi Technical Bulletin" published in 1985, Vol. 59, No. 9 of Mitsubishi Corporation.)
In the above-mentioned DRAM, only about 4 bits are tested simultaneously. Due to this fact, this arrangement is less effective for a large memory capacity exceeding 1M bits. In order to expand this concept, it can be attempted to increase the number of bits to be tested simultaneously. However, this may result in increasing the number of peripheral circuits (such as I/O lines or a maintenance amplifier etc.) and also in increasing the chip size. In addition, even if the above-mentioned increase of the chip size is ignored, it may be assumed that about 16 bits or 32 bits are an upper limit of the number of the bits. Further, in the case of the above-described system in which the sensed outputs, under their non-coincidence condition, become a high impedance, there is no effective sensing means which may be applied when a DRAM is mounted in a printed circuit board etc. Due to this fact, this is not appropriate for a memory testing under its normal condition of application.